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ENGR 250 :: Digital Logic Design :: Winter

Course Number & Title:
ENGR 250, "Digital Logic Design" , 5 Credits
"4 hours of lecture and 3 hours of lab"


Instructor:
Izad Khormaee
www.EngrCS.com
email Izad
360-992-2383 (voice)
Schedule (office hours)


Text Books:
Digital Logic Design by Khormaee
Digital Design by Wakerly (Optional)


Additional Material:
An engineering or scientific calculator such as TI-89
USB thumb drive


Prerequisite
ENGR 120 or CSE 120
USB thumb drive


Course Description and Outcomes:
This is the first course in Digital Design's 2-course sequence. This course covers digital design fundamental and design of digital logic circuits. The student learning objectives are outlined below:

  • Formulate solutions to engineering problems using systematic design methodology
  • Demonstrate understanding of logic families and digital design
  • Understand how to document and analyze design data through EDA software tools
  • Build, test and troubleshoot digital circuits with logic devices and electronics test equipment
  • Implement and optimize logic functions using Boolean Algebra and Karnaugh Maps
  • Design and implement logic circuits to solve practical problems (Sequential/Combinational and Synchronous/Asynchronous)
  • Understand SSI/MSI/LSI logic systems and their applications
  • Recognize timing/triggering faults and utilize latches/flip-flops to minimize them
Course Schedule (subject to change):
  Lecture Topics   Assignments/Evaluations
  Ch 1. Number Systems, Representations and Codes
  • Digital vs. Analog
  • Digital Design Overview
  • Design Methodologies
  • Number Systems (Binary, Octol, Decimal, Hexadecimal)
  • Base Conversions
  • Binary Arithmetic
  • Binary Code
  Lecture Notes

  End of Ch 1 Problems



  Lab #1

  Ch 2. Boolean Algebra, Functions and Minimization
  • Logic Gates
  • Boolean Algebra Postulates & Theorems
  • Boolean Functions and Canonical Forms
  • Function Minimization
  • Algebraic and Karnaugh Map (K-Map) Simplification
  End of Ch 2 Problems



  Lab #2

 
  Ch 3. Analyzing/Designing Combinational logic Circuits
  • Standard Logic and Schematic Layout
  • Designing Logic Circuits
  • Compressing Truth Tables & K-map
  • Glitches & Their Causes
  • Type of Functions and Delays
  • Beyond Standard Logic ( Encoders, PLDs, ...)
  End of Ch 3 Problems



  Lab #3

  Test #1
  Ch 4. Introduction to Feedback Circuits and Sequential Logic Analysis
  • SR Flip-Flops
  • Asynchronous Sequential Logic Issues
  • Finite State Machines (FSM)
  • Additional Flip-Flop Circuits
  • Sequential Circuit Analysis
  • De bouncing Switches
  End of Ch 4 Problems



  Lab #4

 
  Ch 5. Sequential circuit Design and Techniques
  • Synchronous Finite State Machine Design
  • State Assignment Encoding and control
  • Alternate Finite State Machine Design
  End of Ch 5 Problems

  Lab #5

 
  Ch 6. FSM Optimization and Testing
  • Review FSM Design Process
  • FSM Minimization Using Implication Table
  • Design for Testability - Linear Feedback Shift register, In-circuit Tester and Scan Test.
  End of Ch 6 Problems



  Lab #6

  Test #2
  Ch 7. Commercial Digital Integrated Circuits and Interface Design
  • Output Types
  • logic Families
  • XOR Properties and Applications
  • Encoders and decoders(MUX/DeMUX)
  • Adder, Subtractor & Multiplier Design
  • Multiplier Design
  • Arithmetic Logic Unit (ALU)
  End of Ch 7 Problems



  Lab #7

 
  Ch 8. Hardware Description Language
  • History and Steps in HDL Design
  • Architecture and Program Structure
  • Declarations and Operations
  • Structural Design
  • Behavioral Design
  End of Ch 8 Problems



  Lab #8

 
  Comprehensive Final Exam - for schedule visit: www.clark.edu/academics/schedule


Student Evaluation:
  • End of chapter homework draft & review (20 points each)
  • Midterm tests (100 points each)
  • Comprehensive final exam (150 points)
  • Labs' planning, execution and report (20 points/lab)
    Each student is expected to complete the weekly lab assignments during lab time. Even though some labs May be performed as a group, the report is to be completed individually, and due on the following lab period.

  • Note: In order to be eligible to receive a passing grade for the course, all labs and Final Project must be completed (including reports).
Timeliness:
Points are only awarded for tests, quizzes, labs and projects that are completed and delivered on the assigned due dates and times. In all other instances, zero points will be awarded unless the student has made prior arrangements with the instructor.

Course Letter Grade:
Final class letter grade will be awarded based on the total percent of possible points earned by each student as outlined below:

A A- B+ B B- C+ C D F
>94% 94-90% 89-87% 86-83% 82-80% 79-76% 75-70% 69-60% <60%


Conduct:
Students are required to read and follow the Student Responsibilities and Code of Student Conduct as outline in the institute's Catalog.

Cheating/Plagiarism: You are expected to do your own work. Copying or rewriting someone else's online or offline work, having someone else do your work, or cheating in any fashion will result in zero point for that test or assignment in addition to penalties prescribed by college policies. A second offense will result in an automatic 'F' for the class.

Computer or Equipment Misuse: Students are expected to obey the Equipment and Computer Usage Guidelines. Students who misuse the equipments or computers will be expelled from the class and/or lab.

Emergency Exception:
If the instructor judges that the situation warrants special consideration, he may choose to make special allowances in extreme cases.


Disclaimer: The information presented here is deemed to be accurate but we make no guarantee, warranty or representation to its completeness or accuracy. It is your responsibility to independently confirm accuracy and completeness. All rights are reserved.